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https://github.com/SymbiFlow/prjxray-db/blob/master/zynq7/harness/zybo/swbut/design.json#L13
Code was added in #1383 to add an explicit type to the harness. Not sure why this only adds the type fo…
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Looks like there is a failure on the latest commit of https://github.com/SymbiFlow/symbiflow-arch-defs/commit/6575fce443854c489f621e1f7e86da3f5e562494
See the failure at https://source.cloud.google…
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While debugging the Murax design with the interchange format, the following DRC errors were generated:
```
ERROR: [DRC PDRC-131] SLICE_PairEqSame_A6A5_ERROR: Incompatible programming for site SLIC…
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In my masters thesis, I'm creating a comparison framework for SoCs. During bare-metal execution of CoreMark on a simple LiteX SoC I noticed that the CV32E40P only reaches ~0.9 Coremark/MHz. In my lite…
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Equipo 3
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Once the `--verbose` flag was added to fasm2bels in the PR https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1526, a lot of unknown bits is reported. These bits emerge when a design is run through…
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Equipo_4
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There are currently two xc7 vendor CI flakes:
1:
```
ERROR: [Place 30-176] Unroutable Placement! The following clock source instance is driving the following locked load instances. The clock sour…
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https://hydra.vtr.tools/build/798/nixlog/1/tail
```
ERROR: [Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has e…
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https://hydra.vtr.tools/build/837/nixlog/1/tail
```
ERROR: [DRC INBB-3] Black Box Instances: Cell 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$25243' of t…