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I'm using the version hosted in litex-hub's conda repo thing.
I must say, I'm a bit mystified by something. In that version, with the environment set up using conda, tcl scripts using get_count wor…
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Yosys' setparam and getparam (implemented in the [params plugin](https://github.com/SymbiFlow/yosys-symbiflow-plugins/pull/26)) commands should be used in the arch-defs synth.tcl script to recalculate…
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murax_basys test produces RAM64X1D that does not work when trying to load back into Vivado with toplevel_bit.v.tcl
[toplevel.eblif.log](https://github.com/SymbiFlow/symbiflow-arch-defs/files/3408351/…
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Installed the toolchain using Symbiflow_v1.2.0 installer.
While running the compilation for "ram_test" directory in the installation, the read of memory initialization .hex files fails, because the t…
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It would be nice if you could provide a set of pin constraints from the original bitstream compile, such that when translating fasm to bels, the top-level input names could be mapped back to the origi…
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When updating the baslitex test with the newest version of Litex, I have encountered the following assertion failure in VPR:
```
vpr/src/place/place_macro.cpp:135 find_all_the_macro: Assertion 'cl…
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I got your source code from here and install all modules "YOYS, VTR, PRGA" without any error, and done all the process which indicated in the documentation.
```
cd /path/to/prga/
./envscr/instal…
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Hi,
I am a Phd student working on FPGA security. I am trying to use Symbiflow to generate bitstream for Xilinx Artix-7. I am facing multiple problems while installing the toolchain by following th…
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Looks like there is a failure on the latest commit of https://github.com/SymbiFlow/symbiflow-arch-defs/commit/6575fce443854c489f621e1f7e86da3f5e562494
See the failure at https://source.cloud.google…
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This affects PLL phase parameters. Instead of eg. 90.0 it has to be specified as 90000. This makes eg. LiteX generated verilog files not work.
We need to create an XDC plugin that will perform the re…