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I would like to use icestudio in class e.g. to demonstrate the simulation of logic gates. Ultimatively I would like to create logic tables with the students.
I found following two descriptions but …
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**Another feature request:**
gtkwave features a 'save' file that stores the configuration of the user interface at any savepoint. Restarting gtkwave with a previously saved configuration gives you an…
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I'd like to suggest a GTKWave enhancement to support aggregating data from multiple FST files, so they may be presented to the user as if they were from "one file".
Verilator is currently creating …
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The simulation of synthesized netlist is always XXX. as shown in the image.
![postsynth_output](https://user-images.githubusercontent.com/25682001/127743328-b88bcd92-27b1-4636-b8d6-4ed442314c32.png)…
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I do have nested groups in "Signals" view:
![gtkwave-groups](https://user-images.githubusercontent.com/5032806/111876262-3e6b7580-899e-11eb-9d9d-f7127ce6dee9.png)
Although the groups are nested th…
Nic30 updated
2 years ago
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Hi,
I have few remarks for improvements of waveform dumping, IMHO it would be good to include following:
1. Option to enable/disable dumping of internal signals (not only all signals)
2. Opti…
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Simulation output should be visible via a waveform generation interface.
Stubs to do so have been created in commit: `eeaf2192a8e10e7ffbebec8f7ccf62db308d8d11`.
These stubs focus on unrolling a si…
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I'm investigating an issue where a specific write-write-read sequence returns an incorrect result.
My LiteDRAM core is configured for Arty A7 with a 32-bit wishbone port.
I was able to reproduce th…
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http://covered.sourceforge.net/
http://www.asic-world.com/examples/systemverilog/index.html
https://github.com/FPGAwars/FPGA-peripherals/wiki/Asynchronous-serial-receiver-unit
https://verificationa…
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When clicking or trying to edit the text for search, gtkwave keeps selecting the whole word, forcing you to manually intervene to prevent losing the text already there. For instance, suppose you have …