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Hi,
sometime the esp32 will lost his BT connection to the BMS.
So I have found this code to reset the esp32
```
online_status:
name: "status online"
id: bms0_s…
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Affects all tests in `test_force_release`.
```
MODULE=test_force_release TESTCASE= TOPLEVEL=sample_module TOPLEVEL_LANG=verilog \
sim_build/Vtop
-.--ns INFO gpi …
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Create good support for SystemVerilog.
- [ ] https://github.com/hdl/bazel_rules_hdl/issues/132
- [ ] https://github.com/hdl/bazel_rules_hdl/issues/133
- [ ] https://github.com/hdl/bazel_rules_…
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https://wilsonwang.org/2019/10/05/HDL-Editor-Setup/
Rationale:The project intends to provide a simple solution for those who wish to generate structured Verilog HDL code from a GUI and is suitable …
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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I think it would be a nice idea to add the possibility to export to HDL from the CLI. It would allow the integration of Digital in Makefile or build scripts.
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I have encountered three situations that symbolator generates an unexpected symbol.
- Instantiation of a module whose name contains input, such as input_buffer. Symbolator will render this as a por…
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I run the test under windows and find an error. What is the reason?
F:\hdl-js>node bin/hdl-js -g examples/MipsAlu16.hdl -e '[{a: 2, b: 3, op: 2}]' -f dec -c a,b,out
evalmachine.:1
('[{a:)
^^^^^…
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Hi, in docs there're specs for some Velodyne sensors. Maybe someone has also spec for older 64E and 32E? Regards,