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David
is ice40 permanently stalled?
I do appreciate you are heavily committed on other open source initiatives!!
have potential interest and/or project, any chance of a headsup?
thanks ag…
peepo updated
2 years ago
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Hi Guys,
I am currently trying to use the existing LEC module of Yosys to perform Logical Equivalence Checks.
I can't seem to get it working properly.
Is this still work in progress? I am still…
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### Description
Support for RISC-V Core-Local Interrupt Controller (CLIC) (https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc).
### Usage example
Looks like the Core-Local I…
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From reddit here.
First off i've been very interested in this project because the idea of it is very cool, but there seems to be issues that are out of my technical capability (just a graduate stu…
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Replace picorv32 with vexriscv
Remove iob-cache and use vex's cache
Use axi ram for internal memory or remove it for external
Use boot controller peripheral such as in revamp stale branch
…
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While working on #244 I noticed that some designs result in yosys failing on `yosys-abc` call:
```
4.46.18. Finished OPT passes. (There is nothing left to do.)
4.47. Executing TECHMAP pass (map t…
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I'm using riscv-torture to test my RV32IC implementation. For this I create RV32I test cases and build them with `-march=RV32IC`. See https://github.com/cliffordwolf/picorv32/tree/master/scripts/tortu…
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### Description
I have successfully generated GDSII file with open lane for picorv32 with configuration using docker container.
However when I try to get GDSII for Rocket chip with Tiny configuratio…
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* PYNQ version: 2.4 Release 2019_02_21 2382a55
* Board: PYNQ-Z1
* Vivado 2017.4
Until notebook 4 [Packaging-An-Overlay](https://github.com/drichmond/RISC-V-On-PYNQ/blob/master/notebooks/tutorial/…
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In the provided [example](https://github.com/chili-chips-ba/openCologne/tree/main/2.Simple--1--PSRAM) if you change the bit width of `counter` from 6 to any other number the design stops working, UART…