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# RT-Thread For Nuclei RISC-V Processor
## About branch for Nuclei
> **Make sure you have pulled latest changes from desired branch.**
* **nuclei/lts-v4.1.x**: Works for Nuclei RISC-V Process…
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I am currently learning to port the fp16 multiplication of fbgemm to riscv. I found that the fp16 gemm `uses cblas_gemm_compute`, which uses `partition_avx512` to partition the `mb_max=120` rows of ma…
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This first comment just describes the issue(s). Follow-up comments
discuss possible solutions.
Currently the Sail model writes out a log file in ASCII format. Issues:
* Logs can become very lar…
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With a compatibility layer (https://github.com/EESSI/compatibility-layer/pull/204) and software build container (https://github.com/EESSI/filesystem-layer/pull/132 and https://github.com/orgs/EESSI/pa…
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Dear community,
First of all I want to say thank you for creating this project!
I am a total newcomer to everything related to RISC-V and I find it hard to get started.
So here is what I want…
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# Road Map
- [x] profiling
- [x] tbljal insn codegen
- [x] objdump insn with notation (function name & address)
- [x] write tbljal entries into executable file
- [x] csr and its initialization
…
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As I just suggested in the RISCV meeting: We often want to run simulations (typically performance models) for some micro-architecture, say implementing RISCV. Typically we don't want to implement the …
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Romain Dolbeau reported that some modules don't load on RISC-V to the Linux kernel mailing list. The URL of the reported mail is listed below.
https://lore.kernel.org/linux-riscv/1572281840733.3517@e…
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Currently the model doesn't have very clear or rigorous handling of chip reset. I think we should do the following:
1. Rename all of these `init` functions to `reset`. This makes it clear that the …
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If bumping Ariane to include PMP support, we see a kernel panic when attempting to run init.
Moving discussion from #61