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## Describe the bug
`ot/verilog/verilog.cpp` cannot process my verilog demo file...
## To Reproduce
This is my verilog file generated by yosys, which is an inverter:
**./output/inverter.v*…
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In https://github.com/The-OpenROAD-Project/OpenROAD/issues/580 we are chasing an issue where TritonRoute has problems with pin access on some standard cells (in this particular case `sky130_fd_sc_hd__…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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A large number of the verilog files in the standard cells are automatically generated from a `definition.json` file.
### Non-generated files
- `sky130_fd_sc_XX__XXXXXX.specify.v`
- `sky130_fd…
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The output of `open_pdks` is non-deterministic -- IE the exact same input does not produce the exact same output.
This is demonstrated by the PDK being built every 30 minutes and published in the r…
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I've noticed a few examples of the extracted netlist missing the expected connectivity. Manual inspection of the layout seems to show the desired connectivity.
Case 1. `https://github.com/efabless/…
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MPW-8 slot-015 uses `sram_2kbyte_1rw1r_32x512_8`.
The `openram_dff` cell has both `VDD` and `vdd` labels and `GND` and `gnd` labels on the layout.
This extracts to
```
.subckt EL_G3_sky130_f…
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The precheck is detecting lots of DRVs when using the SRAM cell sram_1rw1r_32_256_8_sky130. Is this SRAM cell not mentioned as an exception to DRC, like the other SRAM cells?
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"ext2spice hierarchy off" should flatten a subcircuit until all that is left in the subcircuit are primitive devices.
However, when using the sky130 PDK, it was found that a subcircuit calling the …
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Hi!
im trying to add spice models into the skywater open source pdk
https://github.com/gdsfactory/skywater130/issues/16
what is the format for loading spice simulations in pyspice?
@proppy