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### Test point name
[chip_sw_tap_strap_sampling](https://github.com/lowRISC/opentitan/blob/316831f8c2199f2288dd57ac4aeaec3334b5dfb8/hw/top_earlgrey/data/chip_testplan.hjson#L475)
### Host side c…
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> Note: I'm not sure if this should be an issue or a discussion. I think you can convert between them. Feel free!
I'd like to make two small suggestions to the rule syntax. I realize this is a topi…
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## Steps to reproduce the issue
```
cd tests/svinterfaces
yosys> read_verilog -sv svinterface1.sv
1. Executing Verilog-2005 frontend: svinterface1.sv
Parsing SystemVerilog input from `svinterfa…
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I've got a situation where I'd like to have one SystemVerilog interface instantiate another. I'd like to start a discussion about how we can represent nested interfaces in the IR (as this doesn't curr…
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- Issue Type: `Performance`
- Extension Name: `systemverilog`
- Extension Version: `0.13.4`
- OS Version: `Linux x64 6.2.0-37-generic`
- VS Code version: `1.85.0`
:warning: Make sure to **attac…
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The `tcb_gpio.sv` RTL is a simple GPIO peripheral with `tcb_if.sv` SystemVerilog interface as the system bus.
`tcb_gpio_wrap.sv` is just a wrapper providing simple signals for ports.
The design wa…
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Verible's parser today yields a concrete syntax tree (CST), which views all syntactic tokens (including punctuation and sugar) into as a tree (comments are preserved in a separate array). The CST is …
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The following module verilates fine, works as expected:
```verilog
module InOutMod (input we, inout d);
assign d = we ? 1'1 : 1'bz;
endmodule
```
But put that bad boy inside an interface a…
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steps to reproduce (blanking out function name):
read_systemverilog -defer f1.sv
read_systemverilog -defer f2.sv
...
read_systemverilog -defer f12.sv
read_systemverilog -link
hierarchy -check …
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### Checking the checkers
https://github.com/amiq-consulting/svaunit/blob/master/docs/SystemVerilog_Assertions_Verification_with_SVAUnit_paper.doc
https://www.amiq.com/consulting/wp-content/themes/A…