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Hey -
I am attempting to build a schematic diagram visualizer tool for UHDM designs. To keep the scope small, layout of individual components is decided to be out of scope, at least for now. Howeve…
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(x-post to BSG Manycoree)
It seems unnecessary to have $display statements enabled for every simulation run. Printing information on every run can slow the simulator down, or clog with unnecessary in…
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I will use this issue to keep track of the status of my efforts to add cocotb support to VUnit and receive suggestions and feedback. I am new to VUnit (I haven't used it as a testbenching framework be…
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This is a summary of the discussion at the Hurricane-2 debrief meeting.
Clock muxes and clock division registers should have first-class support in Firrtl. Not sure if this needs an accompanying C…
ben-k updated
5 years ago
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Can it provide completions for common shells? TIA!
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I hope to use printf to print the simulation cycle or specific nanoseconds, but there seems to be no corresponding function in the chisel api. I don't mean `timestamp`, which would print the system ti…
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Hi @michaelgmcintyre ,
While trying to implement this project in Vivado, we found some syntax errors and some ports which were wrongly declared, like in file:
- [ ] https://github.com/opencomputepro…
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Like `icarus verilog`
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It would be nice to show interfacing of a RISC-V simulator with the XLS JIT to demonstrate fast simulation from firmware of a DSLX examples (like #994 or #995).