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## Steps to reproduce the issue
[minitest_bram_36.zip](https://github.com/YosysHQ/yosys/files/4298887/minitest_bram_36.zip)
Run `make bram.edif` to call yosys
Run `make bram_vivado.bit` to call…
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Hello. I am trying to get PyOpenCL to work on my Xilinx FPGA board. I followed all the steps from [nachiket](https://github.com/nachiket) and I got to the part where the environment variables are set,…
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Hi,
I am trying to generate the SHA to write to the eFuse so I can properly activate the secure boot authentication
However using the documented bif file, I am having the following issue:
```
…
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I was just wondering if there's a particular reason that the readme said to use the Chipyard 1.9.1 version, instead of newer versions (eg 1.10 or 1.11). Additionally, if I want to run FireSim with Gem…
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I got involved in new project at the WUT.
We will build wideband MIMO SDR. Probably on the new RFSoC that:
- are pin compatible with ZU25
- offer 8x 10G DACs and 8x 5G ADCs
You won't find any i…
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The CI fails to build `nexpnr-xilinx`: https://github.com/hdl/conda-eda/runs/5446064939?check_suite_focus=true#step:4:1613
```
+ pypy3 xilinx/python/bbaexport.py --device xc7a35tcsg324-1 --bba /ho…
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I there advantage disadvantage of using this adapter vs following this xilinx wiki on cache coherency? https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Cohere…
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This is to track merging of improved Xilinx Zynq-7000 support.
Current set of changes:
- u-boot SPL: boots the system as in secure mode
- u-boot SPL: has different device tree from u-boot prope…
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This one should probably be assigned to Andra. It seems some recent changes to the ObjectFifo are causing an issue for me. The following compiled fine for me a couple weeks ago.
Try to build `refer…