-
When running perf_event_open01 test on Xilinx ZYNQ ZC702/706 board, it fails with the following error:
>
tag=perf_event_open01 stime=1571849199
cmdline="perf_event_open01"
contacts=""
analysis…
-
Hello!
In the xgpiops_polled_example.c, only the Zynq platforms are shown. What is the Output_Pin value for the Versal Development kit's USER GPIO LED? I am having trouble finding it based on the sch…
-
Using v1.10, on Ubuntu 20.04, a project-mode build of U-Boot for the Mars ZX3 with ST3 fails. Full reproduction details below. The initial build done when you choose project mode is actually done on t…
-
**Is your feature request related to a problem? Please describe.**
As far as I can tell the `boot-raw-fallback` slot type does not work for `/dev/mtd*` partitions.
**Describe the solution you'd li…
esden updated
4 months ago
-
1. Could you send email to [xianjun.jiao@ugent.be](mailto:xianjun.jiao@ugent.be) to introduce your self?
**Yes, already sent.**
2. Our image is used directly or you build your own image?
**Your i…
-
`bootgen` has the option `--process_bitstream` which converts a `.bit`-format bitstream to the raw byte-swapped format that is also used in a normal boot image, but without all the headers of a normal…
-
Hi,
my goal is to eventually run a configurable nv_small on Zynq Ultrascale+ while using an nvdc compiled caffe model for inference. I am still a novice in the field of FPGAs, NNs, etc. and have some…
-
Hi,
We have a small data rate ADC and DACs upto 4MSPS which are interfaced with ZYNQ using LVDS channels.
We created the IP which produces ADC Samples over axi-stream interface. Can we use this fram…
-
# Zynq with RedPitaya from scratch: Hello PS World
Noah Hütter's Academic Achievements and a Selection of Electronics and Embedded themed Blog Posts focusing on FPGA, Linux and other fast stuff.
[ht…
-
I am trying to create a way that my software test can notify the simulator for the Programmable Logic (in my case I use QuestaSim) that it has passed or failed the test.
I notice that the reserved …