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Hello,
I made a part using scale(-1,1) in svg pcb file, to do a mirror. In the graphical screen it's properly displayed, but there is an issue. The DRC fails with overlapping things.
I did an expo…
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In OpenRAM when creating an SRAM with the following configuration
```word_size = 16
num_words = 256
words_per_row = 1
tech_name = "sky130"
num_banks = 2
num_rw_ports = 1
num_r_ports = 0
nu…
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Hi all,
I am getting the following error while trying to synthesize my design for implementing NVDLA on an FPGA. I am using the Zynq ultrascale+ family.
_[Project 1-486] Could not resolve non-pr…
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I'm transferring this issue from https://github.com/mp4ra/mp4ra.github.io/issues/136 as it seems to be more related to this group than to registration authority.
I had a question on definitions fo…
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zodat ik mijn applicatielandschap flexibel(er) kan inrichten en registratiecomponenten zowel voor ZGW als voor niet-ZGW kan gebruiken.
Dit geldt i.i.g. voor DRC en BRC die ook buiten ZGW een rol zu…
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I am trying to implement hammerblade example in pynqz2,ultra96v2, and vu47p but it is running out of resources. This issue has been raised in https://github.com/black-parrot-hdk/zynq-parrot/issues/76…
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When I build the GTest integration example in `https://github.com/emil-e/rapidcheck/tree/master/examples/gtest` I get an error:
```
florian@e330:~/ws_github/rapidcheck/examples$ mkdir build && cd …
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There is a single line in both manuals about this being the case. However, Lakeroad can successfully synthesize mul+logic designs, as it isn't outlawed by the simulation model. It would be worth check…
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The file is a video file getting from `camera` plugin and this is the log after compression:
```dart
MediaInfo? mediaInfo = await VideoCompress.compressVideo(
videoFile!.path,
quality: VideoQu…
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### Current Behavior
All Advanced Diffs run for a long time and return errors
### Expected Behavior
Advanced Diffs should run quickly and without errors
### Steps To Reproduce
Configure this env…