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Possible timing issue to look into, processor stops working on the iCE40 UP FPGA when wb_mux is moved back to the EX stage.
rjlv2 updated
5 years ago
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#517 changes the way accesses are done on the CSRs and broke Mor1kx support: lxsim is not responding to user commands.
Command reproduce it:
`rm -rf build && lxsim --cpu-type=mor1kx --opt-level=O0…
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Issue with `yosys` parsing `sha_unit.v`. Requires more investigation.
$ make make shapool_hx8k_ct256.bin
yosys -p 'synth_ice40 -top top_hx8k -blif shapool_hx8k.blif -abc2 -retime' top_hx8k…
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I have a prototype for the high speed data link over EEM at
https://github.com/quartiq/fastino
combined with the Kasli prototype at https://github.com/m-labs/artiq/tree/fastino
This works well (
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## Steps to reproduce the issue
Use [dff.v](https://gist.github.com/promach/ae6d49ebca9b9f209f918622c3b5abe7) or the attached [dff.zip](https://github.com/YosysHQ/yosys/files/3539259/dff.zip)
Ru…
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## Steps to reproduce the issue
I have created an small project to reproduce:
https://github.com/messaging-cells/bug_synth_03
All info to reproduce the bug in the README file.
File with the …
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executing
```./nextpnr-ice40 --json ./ice40/blinky.json --pcf ./ice40/blinky.pcf --asc ./ice40/blinky.asc --gui```
on Mac OS X will launch the PyQT windows, but sub window where that shows the FPGA…
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I just checked out the latest version and it does not pass the tests. I also updated hwtypes and ast_tools.
```
tests/test_syntax/test_sequential.py ..FF.F.F..FF..FF.F.F. [ 42%]
tests…
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I'm looking at the ice40hx8k, and I vaguely understand the blinky example, but it's not really clear from that, nor from the source, how to define and use my own resources and pins.
1. It seems the…
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I followed the build instructions in README.md to build nextpnr but now the command
```bash
nextpnr-ice40 --up5k --package uwg30 --json .build/blink.json --pcf ../pcf/fomu-hacker.pcf --asc .build/…