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```
Info: Slack histogram:
Info: legend: * represents 18 endpoint(s)
Info: + represents [1,18) endpoint(s)
Info: [ 66495, 67276) |+
Info: [ 67276, 68057) |**+
Info: [ 68057, 68838) …
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I got the following error when trying to install **nextpnr-ice40**
```
$ cmake -DARCH=ice40 .
-- The C compiler identification is AppleClang 10.0.1.10010046
-- The CXX compiler identification is…
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After a break in designing the PDP8 I wanted to see roughly how much of a 1K ICE40 my different modules would occupy. After installing the required toolchains and playing around a bit I ran into #16…
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* The B side of a LVDS input is the positive one (https://github.com/sinara-hw/Humpback/issues/9)
* We are not completely following the ice40 recommendation for LVDS output resistor network. They rec…
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I am trying to build this in a Windows environment and I'm getting a failure with timing errors. For tools I am using:
Yosys 0.9 (git sha1 1979e0b1, i686-w64-mingw32.static-g++ 5.5.0 -Os)
nextpnr-ic…
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# Background
Yosys has recently grown the ability to partially infer ICE40 DSP blocks. This works for some Verilog code, but it is not yet at the same level as the proprietary tools when it comes …
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**Issue by [whitequark](https://github.com/whitequark)**
_Sunday Aug 18, 2019 at 13:54 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/172_
----
AsyncFIFO specifies a transparent…
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ice40 has a special carry structure that taps the input of a LUTs, rather than the output:
![image](https://user-images.githubusercontent.com/6740044/61389113-3116f300-a86d-11e9-8c09-2a31204740fc.png…
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Operative System: Windows 10
Issue: Cannot initialize a project. It is using an ICE40HX1K-STICK-EVN board and as soon as I try to start a new project I have that error also. I also noticed that the F…
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Do we require a testbench for the spi_hw? I tried the code with the same ice40 ultraplus board of lattice semiconductor, but my spi was not successful, just wanted to find where I am missing out. Kind…