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Both Verilog linters (Verilator, Icarus Verilog) that syntastic uses supports at least some SystemVerilog, and the only thing that stops .sv file from being checked by both of them is that .sv file ex…
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Current GIT brought me the following error messages:
> main.o: In function `main':
> /home/jiapei/Downloads/hardware/iverilog/main.cc:939: undefined reference to`lexor_keyword_mask'
> /home/jiapei/Do…
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Expected console output from the below is
```
opt1
opt2
```
But I get an error
```
indirect.v:10: warning: macro OPT1 undefined (and assumed null) at this point.
indirect.v:11: warning: m…
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This repository is quickly going to need CI.
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**Is your feature request related to a problem? Please describe.**
This was a previous issue:
#251 by satu0king was closed on Mar 11 0 of 3
**Describe the solution you'd like**
I would like to h…
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Hi,
I'm simulating some open IP and it takes 10us of simulation time (or about 10 minutes of runtime) to get setup. Unfortunately there is no parameter to reduce the setup time, and each time I mak…
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Hi @laforest. I was updating my [Verifying FOSS HDL-synthesizers](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers) project, and there is an error with `Pipeline_FIFO_Buffer.v`. There a…
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I tried to run the JTAG port insertion command but following error caused exiting the process. Is it a bug or something missing at my end?
```Generating LALR tables
WARNING: 183 shift/reduce conflic…
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We've overloaded `$error` etc to allow us to provide a consistent logging mechanism.
Unfortunately this implementation doesn't handle format values appropriately.
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@mithro : According to iverilog output, the first signal in a primitive's pin list must be the output.
Therefore entries like sky130_fd_sc_hd/latest/models/udp_mux_2to1_n/sky130_fd_sc_hd__udp_mux_2…