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laforest
/
FPGADesignElements
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
MIT License
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CAM implementation
#18
pwang7
closed
2 years ago
2
Faster Arbiter_Priority
#17
BartHaagdorens
closed
2 years ago
4
Fix for Arbiter_Priority interrupting every grant at the next clock.
#16
BartHaagdorens
closed
2 years ago
1
fix bug
#15
pwang7
closed
2 years ago
3
fix typo
#14
pwang7
closed
2 years ago
5
Consider adding Verible and/or Surelog to verilinter?
#13
mithro
opened
3 years ago
1
Possible syntax error at Pipeline_FIFO_Buffer.v
#12
rodrigomelo9
closed
3 years ago
2
Missing Width_Extender module
#11
rodrigomelo9
closed
4 years ago
1
Fixed iVerilog warning on the Constant module
#10
rodrigomelo9
closed
4 years ago
0
Fixed iVerilog error on the priority/round-robin arbiter
#9
rodrigomelo9
closed
4 years ago
1
Function body with multiple statements requires SystemVerilog
#8
rodrigomelo9
closed
4 years ago
3
Constant.v:24: warning: @* found no sensitivities so it will never trigger.
#7
rodrigomelo9
closed
4 years ago
2
Fixed Verilator warning on the Binary Carry-In Calculator
#6
rodrigomelo9
closed
4 years ago
1
Verilator complain about Carryin_binary.v
#5
rodrigomelo9
closed
4 years ago
1
Problems with zero or negative widths
#4
rodrigomelo9
closed
4 years ago
10
Gray Code module
#3
isophase
closed
4 years ago
0
Consider deploying to github pages
#2
sajattack
closed
4 years ago
2
Update Constant.html
#1
tudortimi
closed
4 years ago
9