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Hi,
I'm encountering an error while trying to generate the .resc and .repl files expected to be created by Litex for Renode, using Litex's Python files. How can I overcome this issue? Could you prov…
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I'm trying to debug the AXI up-converter as pertaining to the RocketChip DMA -> MEM -> LiteDRAM path, and wanted to use LiteScope with jtagbone for that purpose.
First, I applied the following patc…
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### ❗ Checklist
- [X] I am using the official english version of Slimefun and did not modify the jar.
- [X] I am using an up to date "DEV" (not "RC") version of Slimefun.
- [X] I am aware that issues…
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Right now we require users to build XLS from source, which can take a long time because of some of our larger dependencies [1](#footnote1) (e.g. LLVM, Z3) and requires users to set up Bazel / a build …
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the list forget liteX and migen(nmigen) platform ^_^
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I have tried ./tul_pynq_z2.py --build --doc and i get this error and there is no html files in the doc/_build directory
```
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loadi…
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**Issue by [whitequark](https://github.com/whitequark)**
_Tuesday Sep 10, 2019 at 09:50 GMT_
_Originally opened as https://github.com/m-labs/nmigen-soc/issues/1_
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Let's collect requirements for…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
JL102 updated
12 months ago
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As described in https://github.com/enjoy-digital/litex/issues/1844, the PoC will demonstrates mapping of > 1GB of DRAM to the 64-bit SoC:
![image](https://github.com/enjoy-digital/litex/assets/1450…