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`qr_detector.detect_and_decode_curved` and `qr_detector.detect_and_decode_multi` fails to compile with "method not found".
Though `qr_detector.detect_and_decode` and `qr_detector.detect_and_decode` c…
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Hi nikos,
It´s me again....Finally I manage to download the RISCV GNU TOOLCHAIN, and I was playing with it and trying to understand it...but when I was going to make a simulation, with ModelSim, I …
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I'm trying to run simulation of one of examples: dff. The version of coctb is 1.4.0 (EDIT: was 1.3.2, changed to 1.4.0).
Unfortunately I'm getting following errors:
```
# ** Error: (vsim-3193) Load…
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I am evaluating the Debug Interface with a VHDL testbench. Everything works fine when I use the 32 Bit instruction encoding.
But when I used the compressed instruction set I get unexpected results wh…
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# "Running the testbench with Verilator" isn't working
I followed all readmes provided on this git and tried to run some basic simulations of the cv32e40p with verilator.
It stops with fatal errors …
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My team is interested in using cocotb for cosimulation, but we have our own custom make flow with Questa and Xcelium. It would be helpful to discuss where the VPI needs to be included in the flow (we …
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I have installed Modelsim SE-64 2019.4 on my windows and I intend to run some systemverilog simulation test via vunit in WSL.
When I'm running Vunit examples for verilog, I will get following error…
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Hello,
I'm trying to run .sv files in verilator. I have some difficulties with linking . First i add 'include' include "pulp_interfaces.sv" in ../pulp_soc/rtl/pulp_soc/pulp_soc.sv. And now
```
%…
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I install fusesoc's stable release. fusesoc init is also successful. Following is the output of fusesoc list-cores:
`Available cores:
Core Cache status
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SRQ91 updated
3 years ago
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Both the PCIe testbench and the FC XCVR testbench seems to error out on this part:
```
# ** Error: ../intelFPGA/20.1/quartus/eda/sim_lib/mentor/stratixv_atoms_ncrypt.v(38): (vlog-2163) Macro ` is …