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When I tries to start simulating a black box module contains `$assert` and `$error`, I got the following error:
```bash
Undefined symbols for architecture x86_64:
"sc_time_stamp()", referenced …
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Code below generate verilog file successfully. However seems to be reporting a lot of hierarchy violation messages when line 127 is un-commented.
```package mylib
import spinal.core._
import sp…
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I have a component that I could not simulate because Verilator would not compile the Verilog generated by Spinal. I have a reduced repro case.
Luckily I can naturally work around the error as my co…
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Do you think you will add support for verilator in the future? http://www.veripool.org/wiki/verilator
Is there a way for me to add it (easily) in the meantime?
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Hi,
I am not sure if I am doing anything wrong here but on my platform, the speed benchmark results are fairly inconsistent. I am using a VexRiscv Core on a Genesys2 FPGA running Linux (125 Mhz).
…
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Aloha!
In README.md, under section CPU Generation (https://github.com/SpinalHDL/VexRiscv#cpu-generation) it states that:
>You can find two example CPU instances in:
>
> src/main/scala/vexrisc…
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Hi,
I've been trying to make changes to the fetch unit of Vex Riscv in a way, that no instruction is fetched until we know for certain, that it will be executed. So basically, we wait for the decod…
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If a project contains a space in its path, invoking SpinalSim gives an error:
Example: if the project path is ```~/Projects/HDL/llrf spinal hdl```, running the test SatSum2DSInt gives the following…
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Thanks for your cool work.
The SpinalHDL wiki is stuck at v1.1.1. Maybe we need to keep it updated to the latest version?
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I am getting this error when I am trying to run `./sim.py`:
```
make: Entering directory '/home/natan/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
make: *** No rule to make target '…