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We are using sdram in our FPGA board. Our SDRAM same that you have given project.
So I am working with your code. I want to create axi ip from your code and use it with the microblaze. I cannot port …
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Hello Jim,
I’m trying to compile the `osvvm` and `verificationip` libraries with help of `ghdl`. I’m using archlinux os, along with [aur/ghdl-gcc-git](https://aur.archlinux.org/packages/ghdl-gcc-…
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**Impact**: rtl
**Tell us about your environment:**
*Chipyard Version:*
*OS:*
I try to generate to generate verilog wit the sim/verilator makefile, which has the AXI Slave port available i…
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I have a complex multiplier with two axis inputs. I could not figure out how to use the source in this case. My workaround is to send data manually. Is there a better solution using the source?
My co…
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I have 8 years of experience in VLSI and EDA.
I don't have a lot of experience with FPGAs, I used my de1-soc for my final thesis at the university and haven't used it ever since.
I am very interes…
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In a testbench with multiple checkers at different levels of heirarchy, it would be nice to see the AffirmCount per ID (if possible). I note you currently cannot fetch the Affirmation count per ID, on…
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If transmitting larger packets over fifo in non-blocking mode it comes to over-read error after certain data amount is transmitted.
The proposed solution is to check occupancy and rxLength so that al…
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https://github.com/bespoke-silicon-group/bsg_f1/blob/be0d7b91ebc6028e9e5ba0f7f8b653f4e9ab486d/hdl/axil_to_mcl.v#L1
A description of what this is. Why is there a crossbar? Is it a single link or mul…
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Hi
Change 3e098f567af0a442ae9f3a41b0fcb90f2092daed modifies the behaviour of the check_stream/check_axi_stream function.
The check functions call the pop function one by one. The command queue to …
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As a first step, create a bit file that properly programs the i2c clock generator.
As a longterm solution, add support for a wishbone communication structure to all i2c and spi clients so that they…