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### Description
We are simulating a system that has some internal on-fabric memory and a larger DDR external memory. The external memory is "slower" i.e. there is latency associated with reads (w…
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When I run `spike pk rv64ui-p-add`, it reported
```
bbl loader
couldn't open ELF program: rv64ui-p-add!
```
I can't make sense how to use the riscv-test.
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Hi sir,
For this above issue, can you please provide me the steps to load memtest_shared.bin into board RAM & also procedures to set registers and run memtest86 , i have a RISCV board from si-five.…
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I'm trying to follow the instructions described in [Bare-metal C Program](https://github.com/d0iasm/rvemu#bare-metal-c-program) in README
I got the following errors (OS: Ubuntu 20.10 x86_64)
```
…
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### Description
Support for RISC-V Core-Local Interrupt Controller (CLIC) (https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc).
### Usage example
Looks like the Core-Local I…
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```
/tmp/ccbuxf4K.o: In function `_start':
(.text.init+0x40): undefined reference to `tohost'
/tmp/ccbuxf4K.o: In function `.L0 ':
(.text.init+0x108): undefined reference to `tdat'
/tmp/ccbuxf4K.…
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Hello Team,
I am fairly new to CRIU, and am quite interested in porting it to RISCV by my own but I feel kind of lost as there are lot of touch points. And am unable to wrap my head around the code…
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RVVM is usable as a generic CPU execution engine, not just as a complete machine.
This suggests for working userspace emulation, which runs RISC-V code inside a host process, directly accesses it's m…
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Dear all,
I post this here in riscv-qemu and in riscv-gnu-toolchain.
Can someone explain me simply how to make the user-space hello-world init working in qemu-system-riscv64 :
```
#include
…
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Hi,
Thank you for building this awesome project, I am trying to build the softcore for Icestick and run an example program but I am not able to get any UART output. I verified the core built on the…