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Hi folks,
I managed to get a RISCV32 image built, but qemu seems to ignore `-m` arguments when starting the image, and sets the memory size to 1G.
Is there any way I can increase it to 4G? I'm t…
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In chapter 17.1, it says the upper SEW-XLEN bits are ignored when SEW>XLEN. For example, if SEW=64 and XLEN=32-bit , the result is bit[31:0]. And then if we want to write the 32-bit result to 64-bit…
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Hi,
thanks for this project - I've managed to get Linux booting on a constrained Board (ECP5 based, https://github.com/zeldin/RVCop64, tweaked to use the VexRiscV-SMP CPU) - see attached bootlog.
I …
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The examples shown for the LA and LI insructions only work for RV32.
For RV64, any address at an offset of > +/-2GB won't work with the example shown.
The LI case has the same issue, as does the abs…
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# RT-Thread For Nuclei RISC-V Processor
## About branch for Nuclei
> **Make sure you have pulled latest changes from desired branch.**
* **nuclei/lts-v4.1.x**: Works for Nuclei RISC-V Process…
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from: https://github.com/llvm/llvm-project/commit/5752e3196bc52fdac70e3650abc703570ff6209b
to: https://github.com/llvm/llvm-project/commit/8d468c132eed7ffe34d601b224220efd51655eb3
commit: fbeb177b2b11…
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build steps
```
../configure --prefix=/home/yanyue/rv32imf_zicsr_zifencei_ilp32 --host=riscv64-unknown-elf --with-arch=rv32i_zicsr_zifencei
make
```
qemu steps
```
qemu-system-riscv32 \
-m…
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I have tried to set PATH to `linux_for_riscv_em/output_mmu_rv32/buildroot/output/host/bin/`, I built the Linux kernel and it runs successfully in your emulator.
I think buildroot has built the tool…
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In the case of an RV32 system that supports 34-bit physical addresses, is it not possible to target the upper-most grain? Since the CSR can only hold physical bits 33:2, it's impossible to specify an …
rbohn updated
5 months ago
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参考 [教程](https://github.com/openjdk-riscv/jdk11u/wiki/SPECjvm2008-Benchmark) 方法,开始测试jdk8
当前报错
```
zhangxiang@k9-plct:~/rv32/SPECjvm$ /home/zhangxiang/rv-jdk8u/jdk8u/build/linux-riscv64-normal-core…