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**Describe the bug**
Verilog SubCircuits show a contention error when Project is Re-loaded (load offline)
1. Create any verilog Subcircuit
for eg: create a NOT gate
![image](https://user-images.g…
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Running `./run_using_iverilog_under_linux_or_macos_brew.sh` crashes with error:
```
./run_using_iverilog_under_linux_or_macos_brew.sh: line 53: 54512 Abort trap: 6 vvp a.out >> log.txt 2>&…
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proposition of enhancement:
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From the given input file, the tool can generate a verilog sequence for simulation purpose. This could save time to the designer and e…
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The YosysOptimizer uses the Verilog Emitter to emit code that can be passed to Yosys, then runs a yosys script. It would be a better practice to directly convert to the RTLIL IR and skip that intermed…
j2kun updated
22 hours ago
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https://frankstrickland.github.io/post/verilog/
In verilog statements are executed concurrently, all statements in a module are executed in non-sequential order, and ...
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https://www.edaplayground.com/x/A
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Hi Alex,
Please share the pcie axi slave verilog.we have only pcie axi master verilog
thanks
V.P.Sampath
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When inside a specify block with a parallel_path_description the parser incorrectly handles a +: or -:
This is because the +/-: is a defined operator in the Lexer. The polarity_operator defined insi…
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This is a proposal: let us make ChiselVerify a more generic testing tool also for Verilog and VHDL designs. Something like, but better than, cocotb.
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Could you please add support for highlighting Verilog and System-verilog ?
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Original issue reported on code.google.com by `alertj...@gmail.com` on 26 Sep 2013 at 2:54