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yuri-panchul
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systemverilog-homework
SystemVerilog language-oriented exercises
MIT License
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Macroed testing
#21
samedhi
closed
1 month ago
1
Add README.md in English.
#20
desai-aditya
closed
2 months ago
0
fixed minor testing issues
#19
kevvz
closed
3 months ago
0
Put PASS FAIL first, print INPUT, EXPECTED, ACTUAL per failure
#18
samedhi
closed
3 months ago
0
Crash in 05_01_fifo_with_counter_baseline
#17
atarasenko2
opened
5 months ago
3
Fix typos in state machine isqrt task descriptions
#16
IanBoyanZhang
closed
5 months ago
0
Fix typo in 03_03_serial_divisibility_using_fsm.sv
#15
IanBoyanZhang
closed
5 months ago
0
Linting with Verilator in Linux scripts
#14
max-kudinov
closed
6 months ago
3
Added English instruction for Homework 5
#13
max-kudinov
closed
7 months ago
0
merge
#12
yuri-panchul
closed
8 months ago
0
Fixed typos
#11
max-kudinov
closed
9 months ago
0
Seq hw 2
#10
pradheepkaliraj
closed
9 months ago
0
Finished hw
#9
pradheepkaliraj
closed
9 months ago
1
fix .md url link
#8
yuri-panchul
closed
1 year ago
0
optimized some code in .bat files
#7
Migilint
closed
1 year ago
2
fix path to icarus verilog/gtkwave
#6
EDAMC
closed
1 year ago
2
Нет вывода на экран
#5
flamesky0
closed
1 year ago
1
Upgrade README
#4
yanshtunder
closed
1 year ago
0
Added detection if Icarus Verilog is installed
#3
yuri-panchul
closed
1 year ago
0
Fix typos and add pdf
#2
unaimillan
closed
1 year ago
0
Fix/readme html files
#1
unaimillan
closed
1 year ago
0