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Hi,
I would like to know if [VHDL-AMS ](https://en.wikipedia.org/wiki/VHDL-AMS) support is on the Roadmap?
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Readme mentions Vim as one of the options, but it's not straightforward to me how to do that. Is there a working example on how to set this up with "vanilla" vim + e.g. Ale or any of those frameworks?…
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I am using a public library that has code that can be reduced to this:
```vhdl
package test is
type enum_1_t is (A_e);
subtype enum_2_1 is test.enum_1_t;
end package;
```
This p…
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Ngspice team has recently added two XSPICE devices: `d_process` and `d_cosim`. These devices allows to simulate the component defined as Verilog/VHDL code with analog schematic. It's need to add suppo…
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Hi,
I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition but the compilation fails, saying it can't find neorv32_application_image.vhd. The file is definitely in the right pl…
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clash hash 833ac34b1770f4c4b9ce7fc4d2e132b800ee41c2
Can't provide whole source.
but suspecting problem in usage clash.
I need to calculate filter coefficients( function is designed and works as …
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## Is your feature request related to a problem? Please describe.
Many students use VHDL as their programming language for simulation of different hardware components and for beginners VHDL can be qu…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
2 months ago
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Just like VHDL-2008, VHDL-2019 brings a lot of new features to the language. While some of them are quite out there and probably hard to implement, there are also a few small quality-of-life improveme…
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Produce a full writeup on running the nand2tetris Hack computer on an FPGA. This should be done both with and without the whidl language extensions.
Use mdbook to publish this to github pages.