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Hi,
We have a small data rate ADC and DACs upto 4MSPS which are interfaced with ZYNQ using LVDS channels.
We created the IP which produces ADC Samples over axi-stream interface. Can we use this fram…
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I am trying to create a way that my software test can notify the simulator for the Programmable Logic (in my case I use QuestaSim) that it has passed or failed the test.
I notice that the reserved …
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# Zynq with RedPitaya from scratch: Hello PS World
Noah Hütter's Academic Achievements and a Selection of Electronics and Embedded themed Blog Posts focusing on FPGA, Linux and other fast stuff.
[ht…
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Hi,
my goal is to eventually run a configurable nv_small on Zynq Ultrascale+ while using an nvdc compiled caffe model for inference. I am still a novice in the field of FPGAs, NNs, etc. and have some…
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Hi Pavel,
cool project! I wondered why you didn't choose the LTC22xx family of 2-channel ADCs. There you can find pin-compatible ADCs from 12bit @ 25MSps up to 14 bit @ 105MSps, so people could cho…
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Sorry, if this is an offtopic, i'll move it to maillist if it's so. This is just common suggestions about "full metal runtime.js/nodejs" related to this #42 and this #43 issues.
Besides all feature…
danxn updated
9 years ago
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Dear @dgschwend
I use the HLS generate the FPGA_TOP IPcore , and build the Vivado Block Designer to generate the zynqnet_200M.bit file. But _FIRMWARE confuse me.
1. if I use SDK (cross-compile…
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I am trying to implement the zynq_timestamping solution by porting the existing implementation into ZC702/ZC706 + FMCOMMS5.
Having as reference the Block design of the ZCU102 and AntSDR, I managed to…
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Hi,
I'm sorry to ask here, but I found very few information on this Zynq 7020 / AD9361 SDR on the web.
Could you tell me if it works with [srsRAN](https://github.com/jsroldan/srsRAN) ? srsRan suppo…
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Platform: `Linux 5.4.0-73-generic #82~18.04.1-Ubuntu SMP`
Sourcetrail version: 2021.1.30 64 Bit, database version 25
Each file fails with two errors:
- `no input files`
- `unable to handle compi…