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The following code contains a bug, where signals reference each other in a sort of non-deterministic infinite loop. Currently, IVerilog stalls during the `vvp` execution stage. I believe that it shoul…
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While I am using AxiStreamSink to collect dut out, I have noticed that the signed integer is not being collected. When I collect directly from dut out (without using AxiStreamSink) I am able to collec…
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1.run test case fio_fb.py with config fio_fb_perf.json
2.when run to step random precondition, got assert : random precondition timed out. Failed to complete within 1800 seconds on x.x.x.x
3.in ocp…
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If a resource deployed using SDX VPX provisioning resource gets deleted in the SDX, the provider is not creating the resource again when we do terraform apply. It responds with the following error.
…
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Can be useful for debugging and commissioning. Currently this is only captured in the renishaw encoder struct.
Should also include the inverted encoder value to uninvert the inverted absolute encod…
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In SpinalSim we now have the capability to interact with buses like AXI to read bits from the design. My design currently exposes some SpinalHDL `Bundle`, `Union` and `SpinalEnum` over AXI and the si…
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Looks like SPI signal names are fixed to ['sclk', 'mosi', 'miso', 'cs'] (except for 'cs') and can be only prefeixed. What is the recommended flow to connect to DUT signal names that do not match that…
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One story is about enabling the edge client (EDGAR) with further automotive protocols, i.e. CAN (currently only ETH), and other automotive functionality to communicate/ interact with directly connecte…
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### Issue Description
test_algorithm_config run into failure with non nVidia platform
### Results you see
=================================== FAILURES ===================================
_________…
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I got train images: 0 train labels: 0
I set my folders like this:
––DUTS-TR
——im_aug
———0.jpg
———1.png
——gt_aug
———0.png
———1.png
is there something wrong?
`ValueError: num_samples shou…