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Surelog issue: https://github.com/chipsalliance/Surelog/issues/2556
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Types of interface members are not being translated from UHDM to Yosys' AST. An example of a struct in an interface:
```systemverilog
interface foo;
struct packed {
logic [15:0] bar;
…
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When comparing gate level netlists generated by the Yosys parser and UHDM, it looks like the UHDM plugin is missing an optimization pass for non-observable logic.
sv2v/test/relong/split_ports.v
…
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https://github.com/f4pga/sphinx_f4pga_theme/actions/runs/8317712711/job/22758800810?pr=23
```
/home/runner/work/sphinx_f4pga_theme/sphinx_f4pga_theme/docs/markdown.md:18: WARNING: unknown node typ…
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1. SPRAM inferencing
2. DPRAM inferencing
3. Split support for SPRAM (placing 2 18K RAMs in a 36K block)
4. Asymmetric RAM support for SPRAM
5. Testcases to verify RAM inferencing, Split support &…
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[Reference](https://colab.research.google.com/github/byuccl/digital_design_colab/blob/master/Labs/arithmetic_lab/arithmetic_lab.ipynb#scrollTo=jkKm3WaizMYC)
When running the Compiling the F4PGA Too…
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I'm trying to get a grasp on the source before working on development and I am confused by one thing.
In [xilinx_device.py](https://github.com/gatecat/nextpnr-xilinx/blob/xilinx-upstream/xilinx/pyt…
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I'm having some trouble getting the bsc testsuite to run properly. Running `make check-suite` at the top level ends in a failure
```
...
cleaning /home/lucas/hardware/bsc/testsuite/bsc.verilog/tas…
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Similar to the issue #722 I am seeing that synthesis is failing
```
Project status:
[S] bitstream: bitstream -> /home/navaneeth/Projects/openmpw/CFU-Playground/soc/build/digilent_arty.proj_…
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Hi, everything compiled successfully.
This is the command I ran:
`python3 -mfasm2bels --connection_database ./mydb.db --db_root /home/pc-5/Desktop/fpga_bit_to_verilog/f4pga-xc-fasm2bels/third_par…