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The BIOS does not compare up on the Lattice ice40 HX8K EVB. There are several issues.
I have gotten some of the way here:
https://github.com/niklasnisbeth/litex-buildenv/commit/846fc6193972692f9…
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I have the following in a Migen module:
```py
self.comb += [
# Always valid
self.tx.tvalid_i.eq(1),
# Throw away receiver data
self.rx.tready_i.eq(1),
# Clear an error…
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There are several pins that are missing from some devices such as `CABGA381`, namely Y11, Y12, W4, W5, Y5, and Y6, all of which are used for PCIe in e.g. https://github.com/enjoy-digital/litex/blob/ma…
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What is this file? How was it made? etc....
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**Please DO NOT start working on tasks from this list on your own.** These tasks are very complex, have far-reaching consequences, and require subtle API design. In most cases, I (@whitequark) have a …
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### Issue Details
Hi. We are trying to setup fast-servo with linien in our lab and have encountered an issue while running the `initialize.py` script. It seems to fail to properly initialize the devi…
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Hi.
I just started with migen/LiteX and FPGA.
I want to add an UART to colorlite.py
So I copied and modified the parts from ios_stream.py. Sending four bytes over UART works fine. But it keep on …
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I am working on pure-C implementation for OpenVizsla host software: https://github.com/matwey/libopenvizsla
I've faced the following issue with FPGA firmware last summer.
I have been not able to mak…
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@jbqubit asked me to write about our problems with getting DAC output. This was the only real obstacle for us to finish HT3 currently (because DAC output is required for tests in crate) and to distrib…
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I've noticed that ppx_deriving_yojson has a far more comprehensive testsuite than the other plugins. I think it might be useful if all the various plugin authors contributed to a shared testsuite tha…