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**Is your feature request related to a problem? Please describe.**
I think `MEM_INT_DMEM_SIZE` and `MEM_INT_IMEM_SIZE` should be general variables that should apply even we use exrernal memories i.e.…
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Hi @stnolting
**Is your feature request related to a problem? Please describe.**
About TRNG module, As you stated in datasheet, it's possible to keep enable_i signal low to reduce dynamic power of…
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Hi,
I am exploring iCEBreaker board to run various RISC-V CPUs. I am trying to run the UP5KDemo version of the processor. I am able to synthesize the processor and program the flash . I am able to…
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The [NEORV32 documentation Zfinx extension documentation](https://stnolting.github.io/neorv32/#_zfinx_isa_extension) states:
`Subnormal numbers (exponent = 0) are flushed to zero setting them to +…
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**Describe the bug**
While debugging the OCD interface using a Segger J-Link we've noticed that if we issue a halt request and the core is executing an illegal instructions then the halt request gets…
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I have build the the neorv32 for Nexys 4 DDR FPGA board with the TCL provided - https://github.com/stnolting/neorv32-setups/blob/main/vivado/nexys-a7-test-setup/create_project.tcl with vivado version …
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### Hello everyone!
### Context:
Until now, I synthesized the NEORV32 with *Vivado* and there wasn't any problem. Even I added a module via Stream Link and it worked successfully.
However, I…
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Hi, just wanted to ask how can I convert the core vhd files and the memory vhd files into verilog separately ?
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Hey,
seems like I've run into a regression error. I'm using the latest GHDL version via the provided GitHub action:
```yml
uses: ghdl/setup-ghdl-ci@nightly
```
The latest nightly release (f…
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**Describe the bug**
When performing a CSR read command from a CSR register that is tied to a disabled feature, like HPM counters, the core traps with an illegal instruction.
RISCV spec requires th…