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The following does not error or warn:
```
$ ./bin/clang /tmp/test.c -target riscv64 -march=rv32i -o - -S
```
And it produces code according to the value of `-march`:
```
.text
.…
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Following analysis of the architectural coverage from RISC-DV there are a few small issues to investigate
- [ ] rv32i_misc_cg - Instructions in this group are getting executed but aren't appearing …
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## Bug description
If i understand it correctly espup just reuse the build-artifacts from [crosstool](https://github.com/espressif/crosstool-NG). Currently it installs gcc libs for the following 4 ta…
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wsim --sim vcs rv32gc wally32priv
Error on test rv32i_m/privilege/src/WALLY-spi-01.S result 43: adr = 800061bc sim (D$) 000000ff signature = 000000ae
wsim --sim questa rv32gc wally32priv
runs suc…
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--with-abi=ilp32 is not supported for ISA rv64imafdc
make[1]: *** [Makefile:4549: configure-gcc] Error 1
make[1]: Leaving directory '/Projects/marmik_project/shubhangi.verma/spu32/riscv-gcccd/riscv-…
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Could you add a method to add syscalls to the CPU? Thanks!
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Need to implement and test CSR instructions.
rjlv2 updated
5 years ago
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riscof runs normally for me with GCC 11.x installed. It's slow but usable.
I've been trying to upgrade to GCC 12.2 (specifically 2023.01.31).
riscof appears to hang at
INFO | Running Tests …
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I'm currently trying to get a simulator built to run the Miyamoto-Sprint project. When I run the makefile for the simulator with the verilator switch I get the following output:
`riscv-none-embed-g…
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> quat
shhwhh
[hhhh](ddd)
`add s`