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# [인공지능 가속기 설계] Artificial Intelligence Accelerator Design (Using Zynq-7000 FPGA, CDMA, AXI)
[https://radic2682.github.io/project/hardware%20project/2023/12/08/ai.html](https://radic2682.github.io/…
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Platform: `Linux 5.4.0-73-generic #82~18.04.1-Ubuntu SMP`
Sourcetrail version: 2021.1.30 64 Bit, database version 25
Each file fails with two errors:
- `no input files`
- `unable to handle compi…
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mathworks_zynq_R19.2.1 cant build because it's using
```
BR2_TOOLCHAIN_EXTERNAL_PATH="/opt/Xilinx/SDK/2018.2/gnu/arm/lin
BR2_TOOLCHAIN_EXTERNAL_CUSTOM_PREFIX="$(ARCH)-xilinx-linux-gnueabi"
```
i…
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Rocketchip (@680f3b162047c1ac36390dcdf682815fc0b24ffe) configuration: DualCoreConfig (default, unmodified)
On spike -p2, a bare-metal program is executed by both harts simultaneously.
The rocket…
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hi
I am unable to rectifying the following error please help issues
please mention the steps regarding the solution
U-Boot 2015.01-dirty (Nov 13 2019 - 09:18:31)
Board: Xilinx Zynq
I2C: …
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### Description
I am working in PR #20 to add an example for the Ultra96 board.
The blinky example requires instantiating the PS (processing system) hard IP because the clock is obtained from t…
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Hi @alexforencich ,
First of all, thank you for sharing this wonderful library. I have successfully implemented this library code on SP605 (as I discussed with you earlier). Now, I want to implement …
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hi,
does the hello world app. work on xilinx zynq with arm cortex a9?
Thx,
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After #838 we have the 041 fuzzer reenabled and all bits for Artix.
However for Zynq we are missing some, such as:
CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCO7.CLK_HROW_CK_BUFRCLK_L[0-3]
CLK_HROW…
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Dear all,
I want to ask if it is possible to run it on the 3rd party board with the same zynq ultrascale+ fpga core.
due to my limited experience, i need to generate the wrapper file with the zynq p…