-
@jbqubit asked me to write about our problems with getting DAC output. This was the only real obstacle for us to finish HT3 currently (because DAC output is required for tests in crate) and to distrib…
-
The SymbiFlow project is centered around the support for various FPGA technologies. Many projects that constitute SymbiFlow are not directly related to hardware, however they still might require some …
-
The oMigen simulator had a strange interface where user processes would run after a clock edge, but before synchronous signals assume their new value. Not only it is very hard to use and bug-prone (my…
-
Context:
- In October I created a ticket to discuss an add-in architecture for ARTIQ gateware #147.
- This was discussed on the mailing list on [11/13/2015](https://www.mail-archive.com/artiq@lists.m-…
ghost updated
3 weeks ago
-
while running the command ```make gateware``` got this error
![image](https://user-images.githubusercontent.com/61948628/148894003-feb4c789-fbb4-4862-92e6-2eb60951218d.png)
----------------------…
-
I used the gen.py file to generate a litedram core, and meanwhile a build_xxxx.sh was generated as well.
When I tried to run build_xxx.sh file , it point to a make file in "litex" folder which call a…
-
Using a Memory with 2 ports (both read and write) I get this error with Vivado v2021.1:
```
ERROR: [Synth 8-2914] Unsupported RAM template [.../gateware/test.v:4513]
ERROR: [Synth 8-5743] Unable to…
-
There are many files in J1Sc/src/main/scala defining the circuit. This documentation is an overview of what those files do. For simplicity I deleted the .scala from the file names.
**J1**: This…
-
I've been trying to locate the DFU source code of the orange crab for a while now, without success. Is there a documented, reproducible build of it somewhere so we can instantiate the base bootloader?…
-
Please tell me if I should create this issue somewhere else.
I remember you controlled the LED with PWM driver in Linux.
Could you share the commands you used?
thanks!