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python some module file giving module error how to solve it??? alleast give some file related info in each file
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### Issue description
When I try to install a specific git commit of a repository, pipenv ignores the commit hash and installs the head.
### Expected result
I expect to see the specified comm…
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Hello, I have 10 years of professional experience in VHDL and I am investigating myHDL for my firm as an alternative to VHDL. myHDL looks really interesting, well thought out and polished, but since t…
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I've noticed that ppx_deriving_yojson has a far more comprehensive testsuite than the other plugins. I think it might be useful if all the various plugin authors contributed to a shared testsuite tha…
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Hi,
I'm using MyHDL with Icarus and I have a statement that is:
```
assign bar0_mm_writedata = 32'hdeadbeef;
```
When reading this from my Cosimulation I read "0" on that signal. If I tell…
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There are many files in J1Sc/src/main/scala defining the circuit. This documentation is an overview of what those files do. For simplicity I deleted the .scala from the file names.
**J1**: This…
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What I would like to be able to do in cocotb is basically the equivalent of making a bunch of verilog `wires` and doing something similar to this:
wire [7:0] port1;
wire [7:0] port2;
…
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Hi Alex,
I'm implementing some of my own logics in `port.v` on an AU250 board. I managed to reduce the logic level
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The purpose of this issue is to gather a list of projects that we can use as tests for ghdl's synthesis features.
- https://www.gaisler.com/index.php/products/processors/leon3
- [antonblanchard/m…
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Hi Alex,
Do you have any plan to support BaseRSerdesSource & BaseRSerdesSink in the cocotbext-eth?
And maybe add eth_phy_10g simulation with cocotb in verilog-eth?
Thanks & BR.