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alexforencich
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verilog-axis
Verilog AXI stream components for FPGA implementation
MIT License
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Requesting elaboration on axis_adapter
#34
keegandent
closed
3 months ago
6
Fix set_bus_skew constraint upper bound in axis_async_fifo.tcl
#33
LukasVik
opened
3 months ago
0
axis_adapter incorrect works with parameter S_KEEP_ENABLE = 0 and when input port s_axis_tkeep = 1'b0
#32
pkuzmin
closed
3 months ago
3
Issue with tuser in axis_adapter
#31
immbelgique
opened
4 months ago
5
axis_frame_length_adjust_fifo incorrect works with small header fifo length
#30
derfe4
opened
6 months ago
0
update readme
#29
wlll123456
closed
6 months ago
0
Add explicit python3 prefix to all python paths in test suite
#28
dbarrie
opened
7 months ago
0
Add explicit python3 prefix to all python paths in test suite
#27
dbarrie
closed
7 months ago
0
axis_fifo.v KEEP_ENABLE parameter changes ADDR_WIDTH
#26
erikliljey
closed
8 months ago
2
Allow overriding RAM style in FIFO
#25
tausen
opened
9 months ago
2
axis_adapter lost data
#24
captainliuy
closed
1 year ago
2
modified conditional expressions in axis_fifo to avoid verilator lint…
#23
jameyhicks
closed
1 year ago
0
Rename arbiter module to verilog_axis_arbiter
#21
olofk
opened
1 year ago
1
arbiter module renaming
#20
olofk
opened
1 year ago
0
AXIS Mux Missing first tvalid?
#19
polyee13
opened
1 year ago
11
Questions about Clock Domain Crossing in axis_async_fifo
#22
Yuan-Mao
opened
1 year ago
1
axis_async_fifo write pointer CDC
#18
Basseuph
opened
2 years ago
5
Intel quartus axis_async_fifo constraints
#17
alexisfrjp
opened
2 years ago
2
edge case bug in axis_frame_len.v
#16
guruofquality
closed
2 years ago
1
add `LAST_ENABLE` to axis_arb_mux
#15
lomotos10
closed
2 years ago
2
Just A Question
#14
mikef656
opened
3 years ago
10
Python File simulation idea how to import packages
#13
BansariK
opened
4 years ago
5
Endianness of axis_fifo_adapter
#12
pfrankis
closed
4 years ago
2
FIFO reset
#11
LeChuck42
closed
3 years ago
6
Width mismatch in axis_arb_mux
#10
olofk
opened
4 years ago
0
Fixes
#9
olofk
opened
4 years ago
0
Some questions about axis_async_fifo
#8
Zeks-lzhang
closed
4 years ago
2
module axis_cobs_encode fails to compile
#7
cemkayhan
closed
4 years ago
1
async FIFO timing constraints for Vivado
#6
caryan
opened
8 years ago
2
``ptr_next`` unused in axis_srl_fifo
#5
caryan
closed
9 years ago
1
:bug: Reset grey code read/write pointers to zero on reset.
#4
caryan
closed
9 years ago
0
Python version < 3.3 compatibility
#3
caryan
closed
9 years ago
5
Async FIFO does not reset
#2
caryan
closed
9 years ago
1
Python version < 3.3 compatibility
#1
caryan
closed
9 years ago
1