-
Using KLayout as a spice parser for lctime we noticed some difficulties with include paths starting with "~".
This example with two minimal SPICE files demonstrates the problem:
`top.sp`:
```
…
-
To create things like dynamic loads, one approach is to set a resistor's value equal a voltage, which LTSpice effectively casts volts --> ohms. To achieve this, the resistor's value must be set as `R=…
-
Retrieve an input text netlist file, parse the netlist information, and create the data structure
-
I have a CARRY4 instance in my netlist, where a 3-bit signal is connected to a 4-bit output. This netlist is generated by Vivado.
```verilog
CARRY4 \count_i_reg[12]_i_6
(.CI(\count_i_re…
-
`spydernet.parse` throws a `AttributeError: 'PosixPath' object has no attribute 'readable'` if you provide a PosixPath pathlib.Path object.
-
**Is your feature request related to a problem? Please describe.**
With this, one could automatically generate HW-property checkers to be implemented into FGPA design.
E.g. Design which is too compl…
-
*(This first comment will be updated as the porting efforts evolve and will summarize results so that others can benefit from it.)*
Hi @alexforencich and all,
First off, congrats for an impr…
-
We plan on supporting Lattice Semiconductor devices in 2022. We need to prepare SpyDrNet for this netlist format.
-
Spicelines that are added to a part are not correctly interpreted by the get_component_info method. On some items such as voltage sources, the spice lines are added to the value (such as a voltage sou…
-
| | |
| --- | --- |
| Bugzilla Link | [36087](https://llvm.org/bz36087) |
| Version | 5.0 |
| OS | Linux |
| Attachments | [Clang diagnostic msg](https://user-images.githubusercontent.com/60944935/1…