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# Problem Definition
Currently, the Github action is only set up for notifying the gap analysis repo: https://github.com/RapidSilicon/Gap-Analysis
However, for RTL benchmarks, CI is need to certif…
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> **Describe the bug**
When at least one of the regression tests is run for longer than is default, the test fails. There are two ways it has been broken between v1.2.0 release, and now. I'm going …
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I'm all up and running with the core and having fun putting together a little Slint app, but I've hit a roadblock with the deferred file loading API. This might be a silly question, but I've been star…
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I am using VTR inside OpenFpga to visualize the structure of my entire fabric. I used "--route_chan_width 100" to fix the channel width, and the entire architecture uses line segments of length 4,howe…
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There is a function named "sync_netlists_to_routing." This function synchronizes the results of packing and routing. During the routing, the pin that a net is connected to may change, and this would m…
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Using this openFPGA core (version 1.2.0), I ran into issues where a Save State fails to load and also corrupts the normal in-game Save. I can duplicate this every time, however, I've only found the is…
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Hello,
I have a few questions regarding the SDC constraints for the implementation stage.
I am hardening the individual blocks (sb, cb, grid_clbs, and IO pads) separately. Then I will include all …
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Hi all,
I'm completely getting lost through the tutorials and "full documentation". I really did not know where to request for help except here. (so I'm very sorry if this issue is not like a real is…
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On firmware beta 2, when loading 101 Starships, the title screen flashes and is not comprehensible.
Upon pressing A to start the game blindly, you can only see the bottom-most few rows of pixels, bu…