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Decomposed from #1
To watch a web video on our own hardware, we must build our own hardware.
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![bugs](https://user-images.githubusercontent.com/29387133/101688971-9ef32a00-3a21-11eb-93fa-4e4409d191fd.png)
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I'm currently trying to get a simulator built to run the Miyamoto-Sprint project. When I run the makefile for the simulator with the verilator switch I get the following output:
`riscv-none-embed-g…
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We use some of the extensions (like Zmmul) that for some reason are not supported by compliers. We should generate superset of our internal isa_str that is accepted by gcc or binutills as `isa` valid …
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I am trying to compile a 32bit binary (similar to the ones in $RISCV/generators/riscv-sodor/riscv-bmarks) for running with the SODOR cores. However, if I compile one with riscv64-unknown-elf-gcc, I s…
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The directory at https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu has;
- blackparrot
- cv32e40p
- lm32
- microwatt
- minerva
- mor1kx
- picorv32
- rocket
- serv…
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Hi,
I need help in clearing one of my doubt regarding Bitmanipulation extension. Do we need to specify the version after enabling the extension. Can someone please tell the use of doing the same …
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I was able to generate riscv_arithmetic_basic_test from the testlist using the run.py script. In riscv_arithmetic_basic_test case assembly test files are successfully generated. But I am facing issue…
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I am on a musl-libc based machine. Thus instead of downloading a `x86_64-unknown-linux-gnu` toolchain by `./litex_setup.py --gcc=riscv`, I prefer to compile a custom toolchain by myself. A summary of …
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Perhaps I missed it but does the privileged specification explicitly state that an implementation must implement user (or supervisor) mode in order for the CSRs in the user (or supervisor) space (bits…