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We have started to do some work but we didn't have an issue for it so I'm creating one.
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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The current testing for hardened FSMs is standardized and just blindly injects a fault whilst some standard sequence is running.
There are a couple of issues with this:
1. The sequence may not b…
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Hi, thanks for the good work!
Maybe I missed something, but I couldn't find an example of how to initialize a register value:
```veryl
pub module RegisterFile (
i_clk: input clock,
) {
v…
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I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not know what is goi…
jeras updated
2 years ago
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When Lakeroad is used to synthesize a design with multiple modules, `lakeroad.so` experiences a segmentation fault.
![image](https://github.com/user-attachments/assets/f3e1caaf-022e-4281-a225-98ff…
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I have taken a quick look into supporting the Synopsys VCS simulator.
It looks like similar to Cadence's `cds.lib`, VCS needs a file `.synopsys_vss.setup` for the library name-to-path mapping. http://…
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The current documentation is not sufficiant to describe the diffrences from the existing works. So I think it should be replaced.
This is a candidate for the description in README.md and the top page…
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We have some projects that use recent Microsemi devices and they have stopped providing device libraries in VHDL.
As I understand the intention of the verilog support was to be able to simulate with …
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The purpose of this issue is to gather a list of projects that we can use as tests for ghdl's synthesis features.
- https://www.gaisler.com/index.php/products/processors/leon3
- [antonblanchard/m…