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#### Feature request description
Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL.
![image](https://user-images.githubusercontent.com/94965293/143841769-5fb4e571-1ae…
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Thank you for this great ide. Especially the schematic generation ist a great Feature. An enhancement would be the Option to create the SVG directly from context menu. At the moment there are serveral…
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## Steps to reproduce the issue
Build the microwatt soc. It is a mixed language implementation (vhdl and verilog), so you need ghdl and the ghdl plugin.
```
git clone http://github.com/antonbla…
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Thanks for the awesome configuration
I am a hardware engineer and I use too much of the VHDL and Verilog languages. Unfortunately, both are not supported by NeoVim built-in lsp. I find this language …
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**Feature Description** :
Let user add a list of files for which no errors/warnings should be raised.
**Feature Usecase** :
Defining libraries in "vhdl_ls.toml" which raise tons of errors due…
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Hi, I wanted to ask few questions about the moore-vhdl-syntax. I would really appreciate if you answer.
1. What is the current status?
2. How many of the constructs defined in the LRM is it able t…
m-kru updated
4 years ago
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The issue might be slightly related to #289.
Recent changes to autocomplete have disabled large parts of VSCodes text based intellisense. While the filtering of the autocomplete results of vhdl-ls …
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Hello,
vhdl-linter won’t detect length mismatch on comparing two registers e.g.:
slv_output(13 downto 0)
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Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:
* ~Unscheduled DFCIR~ Closed with #25 and #31.
* ~Scheduled F…
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**Is your feature request related to a problem? Please describe.**
To export verilog the project needs to be opened from a browser, which is hard to automate.
**Describe the solution you'd like**
…