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I got involved in new project at the WUT.
We will build wideband MIMO SDR. Probably on the new RFSoC that:
- are pin compatible with ZU25
- offer 8x 10G DACs and 8x 5G ADCs
You won't find any i…
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### Environment
Architecture: arm64
Operation System: Ubuntu 22.04 (custom image for [Xilinx](https://ubuntu.com/download/amd))
ubuntu-frame: 144-mir2.17.0, with [hardcoded ARGB pixel format](htt…
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## Steps to reproduce the issue
[minitest_bram_36.zip](https://github.com/YosysHQ/yosys/files/4298887/minitest_bram_36.zip)
Run `make bram.edif` to call yosys
Run `make bram_vivado.bit` to call…
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Hello. I am trying to get PyOpenCL to work on my Xilinx FPGA board. I followed all the steps from [nachiket](https://github.com/nachiket) and I got to the part where the environment variables are set,…
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As enabling general AIE configuration through control packets will be a heavy lift, I intend to approach this in phases:
1. As an initial POC, use control packets to program shim DMAs.
2. Use cont…
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I there advantage disadvantage of using this adapter vs following this xilinx wiki on cache coherency? https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Cohere…
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Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
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This is a pretty large task.
Is essence, what we need, is a piece of code (presumably Yocto .bbclass, or standalone tool) that will generate guest configuration files like domd.cfg or doma.cfg. Ma…
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I've been experiencing issues with a modified version of the VCU108/VCU118 designs (all of the modifications were made after the udp_complete module to add packet types, nothing about the PCS/PMA or M…