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I'm running your driver on an xilinx embedded linux (built w/ petalinux 2017.3) and a Zynq Ultrascale device, and when I run the speed test /loopback test, dma_map_sg returns 0 and errors out. My HW i…
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Hi @alexforencich ,
I have seen the file [axi_ram.v](https://github.com/alexforencich/verilog-axi/blob/master/rtl/axi_ram.v), but I didn't see the use of s_axi_wlast.
Could u tell me the reason ?
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Hi Alex,
Where to find a verilog axi4 synthesizable protocol checker?
Thanks,
David
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Hi Clifford,
I might have found a bug in the AXI B-Channel. It is about the handshaking between B_VALID and B_READY. I already did a bugfix.
Next I will post a screenshot (unfortunately this is no…
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Currently the read-compute-write AXI generator only creates a [single set of channels](https://github.com/calyxir/calyx/blob/main/yxi/axi-calyx/axi-generator.py#L658-L667) for the first `seq_mem` in a…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
On page A3-45 (AXI3 write transaction dependencies), the [AXI spec](https://developer.a…
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Hi all,
I am constantly getting the below-mentioned error when I run the following step:
`./tools/scripts/nf_test.py sim --major switch --minor default
`
I am using a ternary match table in my …
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I spent some time today getting the dot-product design working with AXI on real FPGAs. I just manually edited the verilog for now, but I'll document the issues I found so they can be fixed in the gene…
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https://github.com/cpp-lln-lab/localizer_visual_motion/blob/3d9ebfecb08a117db38ec4ea307d52152c8f36d6/subfun/expDesign.m#L254
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I am using a generic 10.1 inch touch screen that is connected to the rpi3 via HDMI/USB. When Zynthian boots, the display shows fine, but the touch screen does not function properly. The top left of th…