-
Hi,
I was updating the meta-de10-nano recipes in order to use the latest Angstrom branch (2018/Sumo) and also the latest de10-nano-hardware release (RELEASE-20180612_19.29.23) here: https://github.…
-
I've been trying to locate the DFU source code of the orange crab for a while now, without success. Is there a documented, reproducible build of it somewhere so we can instantiate the base bootloader?…
-
Dear,
I try to import project in Quartus v.17 web edition (free)
after opening the project, Quartus ask to perform automatically upgrade of some IP
and take an error regarding some tcl script,
Qua…
-
Hi everyone,
I'm currently working on an adapter for interfacing the BlackParrot processor to a LiteX Wishbone bus. Sadly, I didn't find much documentation about what modes and signals the Wishbone…
-
The BIOS does not compare up on the Lattice ice40 HX8K EVB. There are several issues.
I have gotten some of the way here:
https://github.com/niklasnisbeth/litex-buildenv/commit/846fc6193972692f9…
-
Hi,
Is-it possible to add size for the screen RGB.
I would like try a vga controler, and i need a screen with 800*600 pixels.
And is it possible to add others color models (like 444).
Have a g…
-
Hi
I have a trained DNN which weight is extracted on a .h5 file. What's the road map in order to implement this DNN on a FPGA?
-
The Kasli SOC with DIOT adapter resembles Frankenstein creation and has several limitations (not enough LVDS pairs). For this reason we will develop native KASLI SOC DIOT board.
The idea is to use big…
-
Hi,
seems to be that the ntpsec meta layer builds fine but does not run as expected. Once the process is started, even in command line, ntpd hangs right after locking in RAM and never proceeds.
`r…
-
RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…