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after SpinalSim + Verilator windows setup according to https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/
sbt "test:runMain vexriscv.MuraxSim" (using the latest github clone)
I go…
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Hello, can you please publish bitstream for ICEBREAKER board?
It seems to be opensource and extremely well documented:
https://github.com/icebreaker-fpga/icebreaker
Also you already support oth…
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Hi,
I am continuing to learn SaxonSoc's Minimal sample.
I've got VGA (HDMI) from SDRAM working.
I want to output to HDMI, but also externally extract the VGA signal for LCD.
I think SaxonSoC a…
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**Is your feature request related to a problem? Please describe.**
We have achieved riscv-opcodes source of information in terms of opcodes and variables, but we don't have it's outputs, which are th…
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SpinalHDL: 1.10.1
Scala version: 2.12.18
sbt version: 1.9.8
SymbiYosys version: Git 19.02.204
Problem:
- SymbiYosys chokes on "assert(xxx) else begin end"- statements ( maybe not supported? )
…
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First thank you for creating this repository.
I plan on using this to generate many core Forth processors.
You can read more about my plans here.
https://forth.pythonlinks.info
Probably ini…
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Hi there,
Watching this presentation it seems like this Intel Pathfinder for RISC-V tool supports vexriscv32 (at 12:04):
'Intel Pathfinder for RISC-V & OpenHW CORE-V CVA6 Open-Source Core' [http…
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It seems or1k has an timer object built into the CPU core?
litex has its own timer object.
Figure out the following;
- [X] If the inbuilt or1k timer object is available on real litex SoCs? -- **…
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I was trying this: https://github.com/SpinalHDL/VexRiscv#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-and-verilator
But got the following error, I tried Some way to solve it but it didn't w…
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When I ran this command, sbt "runMain vexriscv.demo.GenFull", the following error occurred. Please help. Thanks!
mji@XPS-8930-5:~/VexRiscv/verilator$ sbt "runMain vexriscv.demo.GenFull"
[info] we…