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I want to do compliance test for Swerv EH1 Core using riscof. But I got following error after installing riscof and running "riscof --help"
![Riscof](https://user-images.githubusercontent.com/5841376…
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**Describe the bug**
When a user use `mcumgr-cli` to upload a new file to the device, the upload may stuck in the middle of uploading.
**To Reproduce**
Steps to reproduce the behavior:
1. west b…
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Hi Sir,
I am Shashank V M, a recent college graduate (Bachelors in Electronics and Communication Engineering) from India. We were connected on LinkedIn earlier. I had contacted you on LinkedIn abo…
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INFO: Building simulation model
verilator -f swervolf_0.7.3.vc --trace -Wno-fatal
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/include/swerv_types.sv:58:31: Define or directive not de…
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Swervolf EH1 is very popular RISC-V based core. But In this repo, there is no target for swervolf EH1. Is there any specific reason?
Kindly resolve this issue.
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## Steps to reproduce the issue
Reduced example:
`test.v`:
```verilog
module test;
wire signed [31:0] a_ff;
my_dff #(32) u_my_dff(
.dout(a_ff[31:0])
);
endmodule
```
Yosys:
``…
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Hello all,
I am trying to debug SweRV RISCV RTL v1.9 during simulation using bitbang bridge and openocd in my environment. For this, I have instantiated SimJTAG module in my testbench and connected…
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Hi @olofk,
I'm trying to add new features/operations and make experiments with the SweRV-EL2 core.
So I would like to be able to change the clock frequency and make it independent from the DDR c…
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Hi,
i notice that the PRM says in section 1.3.1 **"In the ‘Decode’ stage, up to 2 instructions from 4 instruction buffers are decoded."**. But i don't think the Decode stage has 4 instruction buf…
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Hi,
I have doubt in the below code of load forwarding logic
https://github.com/chipsalliance/Cores-SweRV-EH2/blob/a95fdb81ea6dc19239cfe2953ef00710a6f1cf2a/design/lsu/eh2_lsu_bus_intf.sv#L404-L41…