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### Description of the Issue
When changing syntax highlighting for VHDL, "std operator" styles do not change except for font size
### Steps to Reproduce the Issue
1. Set theme to DarkMode…
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Hi!,
I found the following issue:
When more than one component is declared in an architecture, the second component uses the last port doxygen comment. (See line 40)
The same issue happens with t…
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Hi,
VHDL grammar is not correct to parse a bus name with attribute part:
```
ck_event
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Hi
I have developed over 100 complex FPGA's in the last 25 years. for these projects I have unknowingly used a similar concept to UVVM with a product called "Testbench_Toolbox". I I am now trying t…
jud43 updated
1 month ago
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After a new Termux installation (from F-Droid), I perform:
```
pkg update && pkg upgrade
pkg install git
git clone https://github.com/hdl/Termux-packages.git
cd Termux-packages/scripts
./base.sh…
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- [ ] Try with GHDL
- [ ] Try with Vivado
Probably easiest to do with firmware, since they include all other files (confirm that).
Vivado: `read_vhdl -vhdl2008 ` should read the files in VHDL …
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When using the VHDL standalone formatter, "else" and "elsif" statements are indented one step too far to the right:
![image](https://user-images.githubusercontent.com/49446589/210272965-da43fdad-e72b…
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I'd like to import modules written in VHDL without hand-written HDLModule wrapper.
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- May help to prevent malware from spreading when testing actual malware
- May make it more extensible. Ie. easy way to clone the repo and get going without dealing with antivirus software, etc, etc.…
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I'm not able to compile the file "sim_waveform.vhdl" using Vivado (Version 2015.2).
I get the following errors:
```
ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/s…