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Hello,
I'm moving away from xsim to verilator and have a big library of GTKWave `.gtkw` files for viewing traces of all my simulations. When I generate trace files both programs emit different scop…
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Ngspice will deprecated ADMS and switch to OpenVAF compiler for Verilog-A models since version 39 https://github.com/ra3xdh/qucs_s/issues/196#issuecomment-1351948449 . It makes possible to implement V…
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int this wiki "https://github.com/openrisc/community-wiki/blob/master/Ubuntu_VirtualBox-image_updates_and_information.mw" i find the image (ftp://ocuser:ocuser@openrisc.opencores.org/virtualbox-image/…
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not real problems:
1. if i use a symbol with the `schematic` attribute, the `netlist.spice` includes both, the `.subckt symname` and the `.subckt schematic`
![double subcircuits](https://github.co…
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Hello, cheng:
Cgra flow is really helpful.When I run the Docker according to the prompts you provided, I can easily perform related operations through the graphical interface, such as generating DFG …
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I am running the generated .sp file using Hspice, but there is no circuit. I cannot find where to modify the library in the .sp file, or which tool I can use to view my .sp file?
The .v file refe…
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Recently, GSoC 2023 was announced. It would be great if a project for Icarus Verilog could be submitted.
I already talked in [#746](https://github.com/steveicarus/iverilog/issues/746#issuecomment-1…
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Currently when outputs are not wanted they must be terminated with named viewers to prevent wiring errors.
To deal with this a "not connected" component which displays as a T termination connection…
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I'm wondering if I am missing a step or if this is a bug:
ngspice (within qucs_s) returns the error:
```
Ngspice started...
warning, model type mismatch in line
nres1 vin vout mod_res_res…
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We have a module that has an AXI interface. It is possible to connect this module to PULPino via its AXI interconnect. How can this AXI peripheral added to the PULPino AXI interconnect. Is there are e…