-
### Is there an existing CVA6 task for this?
- [x] I have searched the existing task issues
### Task Description
AXI spec, dvplan and verification
### Required Changes
Develop an AXI slave agent …
-
Hello everyone：
if this driver is a single DMA hook, I have succeeded.Can it be used in multi-DMA?
This is my device tree.
axi_dma_0: dma@80010000 {
#dma-cells = ;
clock-names = "s_ax…
-
Thanks a lot for this great project! @alexforencich @rodrigomelo9
I am trying to run the `axi-verilog` designs using `verilator`, however, this library does not seem to be compatible with verilator…
-
your axi link is invalid.
And I can not find the axi in your resource file
Where to download the papermachines.axi???
-
I am able to use the fpga_pci.h and fpga_mgmt.h libraries in my code just fine when I run the code as "sudo".
When I run it as a user, I get an error...
It is a simple AXI-LITE peek/poke comman…
-
The clock-domain crossing double-registers used to connect AXI registers to the user's simulink design are liable to miss write events if the axi clock is faster than the simulink clock (user_clk) sin…
-
### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
On page A3-45 (AXI3 write transaction dependencies), the [AXI spec](https://developer.a…
-
https://wmchappy.cn/2015/07/31/jsjl-AMBA/
AMBA 协议交流～
-
I did some experiments using the DirectDMA implementation, which is used for transferring data to and from PE-local memory (BRAM).
I used an ILA directly at the PCIe bridge on the FPGA to look into t…
-
Most of the dma test examples have a block that looks something like this
```
#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#elif XPAR_MIG7SERIES_0_…