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Example (`file.sv`):
```systemverilog
module foo;
enum logic [1:0] {e_reset, e_clear_tag, e_ready} state_n, state_r;
endmodule
```
Execute:
```
yosys \
-p 'plugin -i systemverilog' …
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`Currently support for custom-type with range is limited to single range` message is emitted from [this line](https://github.com/chipsalliance/yosys-f4pga-plugins/blob/24755e3b43400ad25e90fe01cc764a28…
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Hi I am trying to use the bit2fasm.py but it shows that bitread is not found
It was working before but it is not working now.
I ran it in the conda env
`python3 third_party/prjxray/utils/bit2f…
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A lot of the Python scripts are not complying with standard python formatting rules. We should enable tools which check the files are complaint.
Some tools which we should look at are;
- `pep8`
…
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For people packaging, it is useful to refer to a tag or release, as referring to a commit makes it harder to see the rough relative release date.
Currently, the last tag is from almost 3 years ago:…
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I can use surelog to read in .sv and elaborate it, then use the UHDM python VPI / SWIG interface to interrogate it, yay!
Sorry if I'm missing something obvious, but is there a utiltiy to create a .…
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Related to: https://github.com/chipsalliance/yosys-f4pga-plugins/issues/503
TEST:
```
package foo_flags;
typedef struct packed {
logic a;
logic b;
logic c;
} common_flags_t;
e…
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Rather than having yet another repository which needs to be installed along with Yosys, it would be better to have this be part of the [yosys-f4pga-plugins](https://github.com/chipsalliance/yosys-f4pg…
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When running the following example we get the error `hardware/tools/open_road/surelog_testcases/struct.sv:27 Encountered unhandled typespec in process_typespec_member: 'foo_flags::common_flags_t' of t…
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When you uncomment,
```systemverilog
// This one doesn't work
// typedef union packed {
// foo_flags::common_flags_t [3:0][7:0] atype_t;
// padded_fooes_t [3:0][7:0] btype_t;
// } top_f…