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PSF file is attached. [20220829-psf_debug.zip](https://github.com/KenKundert/psf_utils/files/9448854/20220829-psf_debug.zip)
Below is the error I am getting
```
ipykernel_launcher.py error:
…
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It seems I can write something like `m.d.comb += Assert(Past(signal) == 0)`. If `multiclock` is off in the sby file, what exactly is `Past`?
Here's an example. First, `example.py`:
```python
f…
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The recent version of Xyce support now the S-parameter simulation with `.LIN` directive. It's need to provide user an automated way for this simulation type. Currently the S-parameter simulation may b…
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Skipped indexes are missing in VPI AST.
According to [1] skipped index variable should be represented as vpiOperation with vpiOpType = vpiNullOp.
[1]: IEEE Std 1800-2021 "IEEE Standard for SystemVer…
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Back in 2018 Tom Russo noted the LED library doesn't work for xyce. It didn't work for ngspice either.
I altered the library to function. I don't understand why any of the libraries uses "Ohm" cons…
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It seems that occasionally the verilog parser does not properly parse escaped identifiers. It appears to happen specifically when the escaped identifier is used as in i/o when instantiating a module. …
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I have run into a problem in the Verilog parser. When a module is instantiated, the parser expects ports to be explicitly mapped like this:
`my_module instance_one (.one(wire_one), .two(wire_two))`…
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Hello, I am just wondering whether this tool can add a reverse function, say, to convert Tikz code to spice netlist? In this way, the schematic can be written in Tikz, and then sent to Spice for simul…
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I found a few errors in 03-CommonEmitter_flat and 04-CommonEmitter_subcircuited folders. The primary error was R1 is 39K when it should be 39k. After fixing the typo, plots were blank so I had to dele…
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Hello,
I'm using PyLTSpice to run kind of automatic simulations of a circuit for different sets of parameters.
When I'm using
```
LTC = SimCommander("myfile.asc")
LTC.set_parameter('fhp',0.01…