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The Kid Dracula dump from The Castlevania Anniversary Collection doesn't seem to boot up with FCEUX. I've noticed it doesn't work with the MESEN core of Retroarch either. I dumped it using the command…
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**Describe the bug**
Update all does not pull down moonwalker assets. It identifies the missing files, specifically mwalk.rom, mwalkj.rom and mwalku.rom, but does not download them
![missing asset…
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Good morning,
I am trying to build a custom FPGA architecture with some DSP blocks in it but I am not able to make VPR map my test into one of those custom blocks.
As a first test, I am trying to m…
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Hello, I am trying to define and learn how to build different architectures. However, I am facing an Error I don't know how to solve or manage.
OpenFPGA/vtr-verilog-to-routing/vpr/src/tileable_rr_…
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I had a stash to look into dual-port RAMs for the stack and main RAM, using custom RAM definitions that translated to raw VHDL in pipelineC (ram.h). These RAMs would allow for 16-bit reads and writes…
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I just started the download of the alternative required files for CPS2 now for the 10th time. Pocket Sync keeps crashing without any feedback.
It does download a few since the "missing" amount is dec…
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### Version (or build number)
Current
### Steps to reproduce
Hi, I purchased an Analogue dock for my gitd pocket and set it up with various cores. I noticed that there’s a humming sound coming out …
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### Description
I am working with a small FPGA that was generated with the OpenFPGA tool, when I run OpenLane in step 19 the following message appears:
_Tcl_SetObjLength: negative length requeste…
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Hi,
## Description
I have the next issue when running user_project_wrapper process.
I have on each instance of the fpga_top the declaration of vccd1 and vssd1, I consider that connections will …
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### Version (or build number)
0.1.0
### Steps to reproduce
_No response_
### Expected Behavior
_No response_
### Actual Behavior
When I choose R-Type Leo, there's a loading bar and after, nothi…